1 precision edge sy10el34/l sy100el34/l micrel, inc. m9999-031006 hbwhelp@micrel.com or (408) 955-1690 the sy10/100el34/l are low skew 2, 4, 8 clock generation chips designed explicitly for low skew clock generation applications. the internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. the devices can be driven by either a differential or single-ended ecl or, if positive power supplies are used, pecl input signal. in addition, by using the v bb output, a sinusoidal source can be ac- coupled into the device. if a single-ended input is to be used, the v bb output should be connected to the clk input and bypassed to ground via a 0.01 f capacitor. the v bb output is designed to act as the switching reference for the input of the el34/l under single-ended input conditions. as a result, this pin can only source/ sink up to 0.5ma of current. the common enable (en) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the low state. this avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. an internal runt pulse could lead to losing synchronization between the internal divider stages. the internal enable flip-flop is clocked on the falling edge of the divider stages. the internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. upon start-up, the internal flip-flops will attain a random state; the master reset (mr) input allows for the synchronization of the internal dividers, as well as for multiple el34/ls in a system. pin function clk differential clock inputs en synchronous enable mr master reset v bb reference output q 0 differential 2 outputs q 1 differential 4 outputs q 2 differential 8 outputs description pin names features 5v/3.3v 2, 4, 8 clock generation chip precision edge sy10el34/l sy100el34/l 3.3v and 5v power supply options 50ps output-to-output skew synchronous enable/disable master reset for synchronization internal 75k ? input pull-down resistors available in 16-pin soic package rev.: h amendment: /0 issue date: march 2006 precision edge is a registered trademark of micrel, inc. precision edge
2 precision edge sy10el34/l sy100el34/l micrel, inc. m9999-031006 hbwhelp@micrel.com or (408) 955-1690 package/ordering information ordering information (1) package operating package lead part number type range marking finish sy10el34lzc z16-2 commercial sy10el34lzc sn-pb sy10el34lzctr (2) z16-2 commercial sy10el34lzc sn-pb sy100el34lzc z16-2 commercial sy100el34lzc sn-pb sy100el34lzctr (2) z16-2 commercial sy100el34lzc sn-pb sy10el34lzi z16-2 industrial sy10el34lzi sn-pb sy10el34lzitr (2) z16-2 industrial sy10el34lzi sn-pb sy100el34lzi z16-2 industrial sy100el34lzi sn-pb SY100EL34LZITR (2) z16-2 industrial sy100el34lzi sn-pb sy10el34lzg (3) z16-2 industrial sy10el34lzg with pb-free pb-free bar-line indicator nipdau sy10el34lzgtr (2, 3) z16-2 industrial sy10el34lzg with pb-free pb-free bar-line indicator nipdau sy100el34lzg (3) z16-2 industrial sy100el34lzg with pb-free pb-free bar-line indicator nipdau sy100el34lzgtr (2, 3) z16-2 industrial sy100el34lzg with pb-free pb-free bar-line indicator nipdau notes: 1. contact factory for die availability. dice are guaranteed at t a = 25 c, dc electricals only. 2. tape and reel. 3. pb-free package is recommended for new designs. 16-pin narrow soic (z16-2) v cc en nc clk clk v bb mr v ee q 0 q 0 v cc q 1 q 1 v cc q 2 q 2 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 r q ? q r ? q ? r q d r
3 precision edge sy10el34/l sy100el34/l micrel, inc. m9999-031006 hbwhelp@micrel.com or (408) 955-1690 t a = ?0 ct a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit i ee power supply 10el 49 49 49 49 ma current 100el 49 49 49 54 v bb output reference 10el ?.43 ?.30 ?.38 ?.27 ?.35 ?.25 ?.31 ?.19 v voltage 100el ?.38 ?.26 ?.38 ?.26 ?.38 ?.26 ?.38 ?.26 i ih input high current 150 150 150 150 a dc electrical characteristics (1) v ee = v ee (min.) to v ee (max.); v cc = gnd note: 1. parametric values specified at: 5 volt power supply range 100el34 series: -4.2v to -5.5v. 10el34 series -4.75v to -5.5v. 3 volt power supply range 10/100el34l series: -3.0v to -3.8v. t a = ?0 ct a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit t pd propagation delay to ps output clk 960 1100 1200 960 1100 1200 960 1100 1200 960 1100 1200 mr 650 800 1010 650 800 1010 650 800 1010 650 800 1010 t skew within-device skew (2) 50 50 50 50 ps t s set-up time en 400 400 400 400 ps t h hold time en 200 200 200 200 ps v pp minimum input swing (3) 250 250 250 250 mv v cmr common mode range (4) ?.3 ?.4 ?.4 ?.4 ?.4 ?.4 ?.4 ?.4 v t r output rise/fall times 275 400 525 275 400 525 275 400 525 275 400 525 ps t f q (20% ?80%) v ee = v ee (min.) to v ee (max.); v cc = gnd ac electrical characteristics (1) notes: 1. parametric values specified at: 5 volt power supply range 100el34 series: -4.2v to -5.5v. 10el34 series -4.75v to -5.5v. 3 volt power supply range 10/100el34l series: -3.0v to -3.8v. 2. skew is measured between outputs under identical transitions. 3. minimum input swing for which ac parameters are guaranteed. the device will function reliably with differential inputs down to 100mv. 4. the cmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp min. and 1v. the lower end of the cmr range varies 1:1 with v ee . the numbers in the spec table assume a nominal v ee = ?.3v. note for pecl operation, the v cmr (min) will be fixed at 3.3v ?iv cmr (min)i. truth table clk en mr function z l l divide zz h l hold q 0? x x h reset q 0? note: z = low-to-high transition zz = high-to-low transition
4 precision edge sy10el34/l sy100el34/l micrel, inc. m9999-031006 hbwhelp@micrel.com or (408) 955-1690 timing diagram the en signal will freeze the internal clocks to the flip-flops on the first falling edge of clk after its assertion. the inte rnal dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. the outputs will transition to their next states in the same manner, time and relationship as they would have had the en signal not been as serted. en q1 q2 clk internal clock disabled internal clock enabled q0
5 precision edge sy10el34/l sy100el34/l micrel, inc. m9999-031006 hbwhelp@micrel.com or (408) 955-1690 16-pin soic .150" wide (z16-2) rev. 02 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this datasheet is believed to be accurate and reliable. however, no responsibility is as sumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant inj ury to the user. a purchaser s use or sale of micrel products for use in life support appliances, devices or systems is at purchaser s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2006 micrel, incorporated.
|
